We all try to do our part and save energy by using less light and air conditioning or unplugging unused electronics. This is because saving energy also helps cut down on carbon emissions generated from thermal power, a driving force behind climate change.
It’s just like how Samsung creates low-power memory chips to reduce the energy used in data centers.
From AI to 5G, the Internet of Things (IoT), and self-driving cars, chips are leading the Fourth Industrial Revolution. As the technology within these chips becomes more advanced and complex, the process technology used to make these chips is also undergoing huge developments. In particular, we see devices getting smaller and so chips are designed to even smaller to match, which is exactly why ultra-fine processing technology has become so important.
Samsung’s innovative technology isn’t just to make
products, but to also help the environment. We’ve
used 3D stack packaging technology X-Cube on
system semiconductors for the first time in the
industry. X-Cube allows you to vertically stack multiple wafers into a single chip, so you can fit a high-capacity memory solution while decreasing the chip’s overall size.
This allows clients to have more freedom in their designs, and it also dramatically increases data processing speeds and energy efficiency, enhancing performance and lowering the effect of energy on the environment. In addition to X-Cube, we continue to innovate and evolve to create a sustainable environment. By powering everything from AI and 5G to IoT and self-driving cars, we’re pioneering the Fourth Industrial Revolution.
Planar
Structure
3D Structure,
FinFET
Chips are made of multiple transistors, which is an electrical component that can either amplify current flow or act as a switch to control it. GAA (Gate-All-Around) is one type of transistor.
When voltage is applied to the gate, current flows through the channel from the source to the drain. In a planar or 2D structure, its main limitation is that the transistor’s gate and channel are connected on one side. If you try to reduce the size of the transistor to make a small, low-power chip, the distance between the source and drain becomes too close and the gate doesn’t work. There were also limits in lowering the operating voltage, like leakage currents in short channels.
To improve on this, we developed FinFET, a transistor with a 3D structure. It’s named after the structure’s shape of a fin, which is why it’s also called a fin transistor. We built this on the idea that as the side where the gate and channel connect becomes wider, it becomes more efficient. With a 3D structure, FinFET increases the area where the two meet to three sides, increasing chip performance. But we discovered that FinFET also had a limit — it was unable to reduce the operating voltage during the process past 4nm.
Planar
Structure
3D
Structure,
FinFET
Chips are made of multiple transistors, which is an electrical component that can either amplify current flow or act as a switch to control it. GAA (Gate-All-Around) is one type of transistor.
When voltage is applied to the gate, current flows through the channel from the source to the drain. In a planar or 2D structure, its main limitation is that the transistor’s gate and channel are connected on one side. If you try to reduce the size of the transistor to make a small, low-power chip, the distance between the source and drain become too close and the gate doesn’t work. There were also limits in lowering the operating voltage, like leakage currents in short channels.
To improve on this, we developed FinFET, a transistor with a 3D structure. It’s named after the structure’s shape of a fin, which is why it’s also called fin transistor. We built this on the idea that as the side where the gate and channel connect becomes wider, it becomes more efficient. With a 3D structure, FinFET increases the area where the two meet to three sides, increasing chip performance. But we discovered that FinFET also had a limit —
it was unable to reduce the operating voltage during the process past 4nm.
With GAA transistors in ultra-fine circuits under 3nm, the gate wraps around all four sides of the channel to have more control over the current flow. This is why we’ve been able to achieve higher power efficiency.
Planar FET
MBCFET™(Nanosheet)
FinFET
GAAFET
(Nanowire)
It was difficult and complex to maintain sufficient current on a thin wire channel with a 1nm diameter, so our MBCFET™ makes this process easier with layers of long, thin nanosheets to improve performance and power efficiency.
Compared to a 7nm FinFET transistor, we reduce the area of the chip’s logic area by 35%, consume approximately 50% less energy and see about a 30% increase in performance.
35%
Reduction in
logic area
50%
Reduction in power
consumption
30%
Improvement in
performance
The next generation of high-performance chips for AI, big data, self-driving cars and IoT must use low-power technology for the sake of the Earth. We are doing all we can to overcome the limits of technology and enhance its process competitiveness of low-power semiconductors.
The chip industry can be divided into roughly two categories: fabless and foundry. A fabless is a company that doesn’t have a fabrication plant, which is where chips are actually manufactured. Instead, they focus on developing ideas and design technologies. Foundries, on the other hand, are companies with production facilities dedicated to manufacturing chips.
At Samsung Foundry, we handle the entire chip manufacturing process, including the process technology, packaging and testing. Our specialty is ensuring each area, down to infrastructure, quality, support and ecosystem partners, is like an orchestra, working in sync in order to create our best chips.
To turn ideas into reality, fabless companies need a foundry’s exceptional process technology. As chip design technology is refined to create smaller yet better-performing devices, process technology must also be developed. We are solidifying Samsung Foundry’s leadership in ultra-fine processes with Extreme Ultraviolet (EUV) technology.
Making chips requires carving extremely fine circuit patterns on a wafer, a thin disk that’s used to make integrated circuits. The more chip elements that are placed in this small 300mm or 200mm wafer, the higher the performance.
The wavelength of EUV is 1/10 or less shorter than existing argon fluoride (ArF), creating finer patterns, which not only improves the performance and power efficiency of the semiconductor, but also reduces process steps when forming patterns of the same size. This not only enhances chip performance, but also reduces the number of steps within the process — increasing productivity while cutting down on the energy consumed by the end products.
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