Find the optimal for the best. Part 1

Samsung Foundry will present a paper on the design technology co-optimization, which is to optimize the PPA of 3-nano process with GAA transistor application, that is, the DTCO, at the CICC (Custom Integrated Circuits Conference) to be held from April 24 to 27, 2022. The object of this posting is for better understanding of the paper regarding 3nm GAA technology which is scheduled to be mass-produced soon. 1. What is a transistor and why do we want it to be smaller? A semiconductor chip is an aggregate of numerous transistors. So, before we go into details, let’s talk about transistors which is the basis for semiconductor chips. Transistor is a small switch. As a switch operation refers to the entire process from pressing the switch to turning on and off a light using current, rather than to the simple pressing of the switch, a transistor operation refers to the process up to a stage where current flows when the transistor is turned on and current does not flow when the transistor is turned off. Voltage is the key force of turning on the transistor. When the passage for current flow is opened through voltage, the current flows where voltage is high to where voltage is low in its passage. It is like how water flows from where pressure is high to where pressure is low on a channel when the sluice is opened with force. Transistors are divided into two types, NMOS and PMOS. The Si field of transistor (gray area in Fig. [1]) where the absolute value of voltage is high called drain and the field with low value is called source. Refer to Fig. [1] and Fig. [2]

If so, why do we want to make transistors smaller and put a larger number of transistors into single chip? As explained earlier, a transistor is in either an on or off state. Assuming the transistor on state as 1 and the off state as 0, numerous binary codes comprised of 0 and 1 can be expressed through a transistor. Also, various calculations can be run using the binary codes. With these calculations, various functions can be implemented. A smaller transistor enables us to implement more diverse functions or make smaller chip with the same performance level. 2. Does a transistor only need to be small? Then, does a transistor only need to be small? Let’s take the example of a switch again. If an unnecessarily large amount of force is required to turn on and off a switch, we cannot say the switch is a good switch. Likewise, a transistor that requires an excessively large amount of voltage to let the same amount of current flow cannot be considered as a transistor with good performance. If light comes on late when the switch is turned on, or if light continues to be on when the switch is turned off, the switch is not a good switch, either. In the case of transistors, we say the ones with low speed or that let leakage current flow are transistors with low performance. 3. What are the conditions for the best transistor? If so, a good transistor is one that is small and uses a lower amount of power with high performance. Three conditions are called PPA (performance, power, and area). Technologies have been continuously developed for high-performance, low-power, and small-area transistors. 4. Leading increase in PPA benefits through transistor structure change For the best PPA, we have been not only making transistors smaller, but also changing the structure. In a transistor, current flows through the joint surface between the gate and Si (gray area) in Fig. [1]. We call this passage a channel. We changed the structure to make the channel shape more effective. As in Fig. [3], we have led three types of structural change. As the channel width and the number of sides increased, the ability of the gate to control channel also improved. With planar FET, in particular, as the size becomes smaller, the distance between drain and source, that is, the channel length, decreases, resulting in unwanted effects (short channel effects). We solved this problem by developing the FinFET structure to allow gate to wrap the channel and this could improve its control. In addition, we expanded the current flowing passage by increasing the channel width which allows more amount of current can be flew. Moreover, as for GAA, it is in the sheet structure with the fin of FinFET (area where Si field raised up as a fish fin) is laid on the side. Piling up these sheets vertically, we can make a larger amount of current flow in a transistor with the same horizontal area.

5. Samsung’s GAA (MBCFET™), leading the foundry industry

A. Efficient structure of Samsung’s GAA As shown in Fig. [4], GAAs are structurally divided into two types, the wire type, and the sheet type. For the nano-wire GAA, a larger number of wire layers had to be piled up to increase the total channel width, and this made the process even more complicated. To overcome this problem, we adopted GAA, MBCFET™ in a sheet-type structure with a greater width, rather than wire.

B. Strengths of MBCFET™

i. Lower voltage and greater efficiency! Low operation voltage and high current efficiency Power (power consumption) is calculated by multiplying the transistor-applied voltage with the current flowing. The voltage required for transistor operation is called Operating Voltage. We have been making continuous efforts to increase power efficiency by lowering the operating voltage. The concept is similar to how a switch that can turn on a light using a smaller amount of power is more efficient. For MBCFET™, we improved the on-off characteristic (on and off control ability) through a structural change to make all four sides a channel. As with the case of a faucet with improved functionality turning off water using only a small amount of power, the improvement of the on-off characteristic enabled transistors to properly operate even at low voltage. As a result, the operating voltage was lowered, which brought higher power efficiency.

ii. As you want it! High flexibility We need to make transistors with different amounts of current flowing according to design. To adjust the amount of current, the channel width needs to be either increased or decreased. With FinFET structure, the height of the fin that is surrounded by the gate cannot be adjusted. Therefore, to increase the overall channel width, we used a method to increase the number of fins in the horizontal direction. This method, however, only enabled adjustment of the discontinuous channel width. This is because, when the channel width of a fin surrounded by the gate is α, the width can be decreased or increased only in the multiples of α. Not like FinFET height, MBCFET™ allows continuous adjustment of the channel width like Fig[6] by controlling sheet width.

6. DTCO, a process to find the optimal Although all PPA are improving as a structure change, it is challenging enough to use these benefits. This is because chip where numerous transistors are gathered, the design placement affects these PPA and performance, power, and area are in tradeoff. For instance, even a small switch cannot be closely placed if there is a wall between them. Also, more switches with longer and more complicated cables increases resistance and decreases speed. If we cannot have them all at once, we have no choice but to find the optimal condition under the given circumstances. We must find a method to reduce size without lowering performance, a method to improve performance in the same size, or a method to produce the same performance using a small amount of power. We call the process of finding the optimal from the perspective of both process and design DTCO (Design-Technology Co-Optimization). Samsung’s GAA MBCFET™ has a great strength in terms of the optimization process, the DTCO. We will learn about which DTCO-wise strengths Samsung’s GAA MBCFET™ has, and how Samsung Foundry is approaching PPA optimization using the strengths of MBCFET™ by looking into the paper that will be presented at the CICC next week.